Memory systems often use Error Correction Coding (ECC) in order to increase data storage reliability and reduce the likelihood of read errors. For example, U.S. Pat. No. 7,599,235, whose disclosure is incorporated herein by reference, describes an error correction system and method operable to identify and correct a memory module disposed within a computer memory system. In one embodiment, the memory system comprises a first memory module and a second memory module, each comprising a plurality of memory devices; and a memory controller operably coupled to the first memory module and the second memory module. The memory controller is operable to use an ECC word, comprising data and redundant data, to detect module-level errors in the first and second memory modules.
U.S. Pat. No. 5,134,616, whose disclosure is incorporated herein by reference, describes a Dynamic Random Access Memory (DRAM) having on-chip ECC and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section, and has been optimized to maximize signal while reducing soft errors.
U.S. Pat. No. 7,447,950, whose disclosure is incorporated herein by reference, describes a memory system in which an ECC circuit is not inserted on a data path for data writing/reading. The ECC process is performed during the cycle of normal data reading/writing process, in such timing that it does not conflict with the data reading/writing process in order not to cause a substantial delay in the data writing/reading process.
U.S. Patent Application Publication 2009/0251988, whose disclosure is incorporated herein by reference, describes a memory system, memory interface device and method for a non-power-of-two burst length. The memory system includes a plurality of memory devices with non-power-of-two burst length logic and a memory interface device including non-power-of-two burst length generation logic. The non-power-of-two burst length generation logic extends a burst length from a power-of-two value to insert an error-detecting code in a burst on data lines between the memory interface device and the plurality of memory devices.